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HP-Machine-Feature

Two and a half years ago, HP (now HP Enterprise after the visitor split up) revealed a new, revolutionary computer architecture it dubbed "The Machine." This new computing platform would combine cut-edge and nonetheless unproven technologies like memristors, silicon photonics, and truly massive amounts of addressable memory. HPE was forced to dial dorsum some of its ambition when it proved too difficult to bring the entire project to market place all at the same fourth dimension, only information technology refused to give up on the idea of what it calls "Retentivity-Driven Computing."

Today, HPE is announcing that it has demonstrated the major components of this new type of system, admitting in prototype form. The Automobile as currently constituted consists of:

  • Compute nodes accessing a shared pool of Fabric-Attached Retention
  • An optimized Linux-based operating system (OS) running on a customized System on a Scrap (SOC)
  • Photonics/Optical communication links, including the new X1 photonics module, are online and operational
  • New software programming tools designed to take advantage of abundant persistent retentiveness.

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The Machine (well, one "blade" of information technology, anyway). The DIMM slots are filled with NAND Flash; HPE wants to transition to lower-latency retention that competes directly with DRAM in the side by side few years.

HPE has previously shown off some of these components, like its X1 silicon photonics module. The X1 module is capable of transferring information at upwardly to ane.2Tbps (150GB/s of bandwidth) over a 30-50 meter distance. HPE has also demonstrated silicon photonics technology that can motility data up to 50 kilometers (30 miles) at 200Gbps. HPE's major goal with The Car is to create a system in which non-volatile retentivity (NVM)serves as a truthful DRAM replacement, offering at least equivalent latency with drastically reduced power consumption and depression-latency optical interconnects.

Customers will nonetheless accept the option to deploy The Machine as a conventional arrangement but HPE'south plan is to offering huge pools of NVM that can be shared across many SoCs. While the diagrams below but refer to CPUs, there's no reason this model couldn't exist extended to other types of accelerators — vector processors like Intel'southward Xeon Phi or GPUs from AMD and Nvidia could at least theoretically be paired with HPE's new architecture. The following slideshow steps through some of HPE's pattern elements, and the benefits it expects to offer with The Machine compared to traditional systems. Images can be clicked to enlarge them in a new window.

When HPE appear that it would re-purpose The Machine's design around conventional technology in mid-2015, it seemed to imply that the project's groundbreaking potential had been largely buried below fiscal realities and the slow footstep of technological innovation that characterizes mod semiconductor development. Today, I have to admit that this dismissal was premature. HPE may not be planning to commercialize memristor engineering in the near term, but The Machine is more a conventional server with a huge amount of RAM, and the visitor's work on low-latency not-volatile memory and optical interconnects could take pregnant implications for HPC and Big Data problems for years to come up. The Machine won't debut equally a unmarried organization with all-new technologies but should transition to new memory standards as they get bachelor. This might make it a impact less exciting on launch, but should lay the groundwork for a long-term virtuous bike of improved performance and reduced power consumption, up to and including (eventually) exascale-class deployments.